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| LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier August 2000 LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF412 dual is pin compatible with the LM1558, allowing designers to immediately upgrade the overall performance of existing designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage and drift, low input bias current, high input impedance, high slew rate and wide bandwidth. Features n n n n n n n n n n n Internally trimmed offset voltage: 1 mV (max) Input offset voltage drift: 10 V/C (max) Low input bias current: 50 pA Low input noise current: Wide gain bandwidth: 3 MHz (min) High slew rate: 10V/s (min) Low supply current: 1.8 mA/Amplifier High input impedance: 1012 Low total harmonic distortion 0.02% Low 1/f noise corner: 50 Hz Fast settling time to 0.01%: 2 s Typical Connection Connection Diagrams Metal Can Package 00565642 00565641 Ordering Information LF412XYZ X indicates electrical grade Y indicates temperature range "M" for military "C" for commercial Z indicates package type "H" or "N" Order Number LF412MH, LF412CH or LF412MH/883 (Note 1) See NS Package Number H08A Dual-In-Line Package 00565644 Order Number LF412ACN, LF412CN or LF412MJ/883 (Note 1) See NS Package Number J08A or N08E BI-FET IITM is a trademark of National Semiconductor Corporation. (c) 2004 National Semiconductor Corporation DS005656 www.national.com LF412 Simplified Schematic 1/2 Dual 00565643 Note 1: Available per JM38510/11905 Detailed Schematic 00565632 www.national.com 2 LF412 Absolute Maximum Ratings (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Note 11) LF412A Supply Voltage Differential Input Voltage Input voltage Range (Note 3) Output Short Circuit Duration (Note 4) Continuous H Package Power Dissipation Continuous N Package LF412 (Note 12) Tj max jA (Typical) Operating Temp. Range Storage Temp. Range Lead Temp. (Soldering, 10 sec.) H Package (Note 5) 150C 152C/W (Note 6) N Package 670 mW 115C 115C/W (Note 6) -65CTA150C -65CTA150C 22V 38V 19V 18V 30V 15V 260C 1700V 260C 1700V ESD Tolerance (Note 13) DC Electrical Characteristics (Note 7) Symbol VOS VOS/T IOS Parameter Input Offset Voltage Average TC of Input Offset Voltage Input Offset Current VS=15V (Notes 7, 9) IB Input Bias Current VS=15V (Notes 7, 9) RIN AVOL Input Resistance Large Signal Voltage Gain VO VCM CMRR PSRR IS Output Voltage Swing Input Common-Mode Voltage Range Common-Mode Rejection Ratio Supply Voltage Rejection Ratio Supply Current VO = 0V, RL = 3.6 5.6 3.6 6.5 mA (Note 10) 80 100 70 100 dB RS10k 80 Tj=25C VS=15V, VO=10V, RL=2k, TA=25C Over Temperature VS=15V, RL=10k 25 200 15 200 V/mV V V V dB 50 Tj=25C Tj=70C Tj=125C Tj=25C Tj=70C Tj=125C 10 12 Conditions Min RS=10 k, TA=25C RS=10 k (Note 8) LF412A Typ 0.5 7 25 Max 1.0 10 100 2 25 50 200 4 50 Min LF412 Typ 1.0 7 25 Max 3.0 20 100 2 25 50 200 4 50 10 25 12 Units mV V/C pA nA nA pA nA nA V/mV 200 200 12 16 13.5 +19.5 -16.5 100 12 11 70 13.5 +14.5 -11.5 100 Note 2: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. AC Electrical Characteristics (Note 7) Symbol Parameter Amplifier to Amplifier Coupling SR GBW Slew Rate Gain-Bandwidth Product Conditions Min TA=25C, f=1 Hz-20 kHz (Input Referred) VS=15V, TA=25C VS=15V, TA=25C 10 3 15 4 8 2.7 15 4 V/s MHz LF412A Typ -120 Max Min LF412 Typ -120 Max dB Units 3 www.national.com LF412 AC Electrical Characteristics (Note 7) Symbol THD Parameter Total Harmonic Dist (Continued) LF412A Min Typ 0.02 Max Min LF412 Typ 0.02 Max % Units Conditions AV=+10, RL=10k, VO=20 Vp-p, BW=20 Hz-20 kHz TA=25C, RS=100, f=1 kHz TA=25C, f=1 kHz en in Equivalent Input Noise Voltage Equivalent Input Noise Current 25 0.01 25 0.01 Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: Any of the amplifier outputs can be shorted to ground indefintely, however, more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded. Note 5: For operating at elevated temperature, these devices must be derated based on a thermal resistance of jA. Note 6: These devices are available in both the commercial temperature range 0CTA70C and the military temperature range -55CTA125C. The temperature range is designated by the position just before the package type in the device number. A "C" indicates the commercial temperature range and an "M" indicates the military temperature range. The military temperature range is available in "H" package only. In all cases the maximum operating temperature is limited by internal junction temperature Tj max. Note 7: Unless otherwise specified, the specifications apply over the full temperature range and for VS=20V for the LF412A and for VS=15V for the LF412. VOS, IB, and IOS are measured at VCM=0. Note 8: The LF412A is 100% tested to this specification. The LF412 is sample tested on a per amplifier basis to insure at least 85% of the amplifiers meet this specification. Note 9: The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, Tj. Due to limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj=TA+jA PD where jA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 10: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = 6V to 15V. Note 11: Refer to RETS412X for LF412MH and LF412MJ military specifications. Note 12: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside guaranteed limits. Note 13: Human body model, 1.5 k in series with 100 pF. Typical Performance Characteristics Input Bias Current Input Bias Current 00565610 00565611 www.national.com 4 LF412 Typical Performance Characteristics Supply Current (Continued) Positive Common-Mode Input Voltage Limit 00565612 00565613 Negative Common-Mode Input Voltage Limit Positive Current Limit 00565615 00565614 Negative Current Limit Output Voltage Swing 00565616 00565617 5 www.national.com LF412 Typical Performance Characteristics Output Voltage Swing (Continued) Gain Bandwidth 00565618 00565619 Bode Plot Slew Rate 00565620 00565621 Distortion vs Frequency Undistorted Output Voltage Swing 00565622 00565623 www.national.com 6 LF412 Typical Performance Characteristics Open Loop Frequency Response (Continued) Common-Mode Rejection Ratio 00565624 00565625 Power Supply Rejection Ratio Equivalent Input Noise Voltage 00565626 00565627 Open Loop Voltage Gain Output Impedance 00565628 00565629 7 www.national.com LF412 Typical Performance Characteristics Inverter Settling Time (Continued) 00565630 Pulse Response RL=2 k, CL=10 pF Small Signal Non-Inverting Small Signal Inverting 00565636 00565637 Large Signal Inverting Large Signal Non-Inverting 00565638 00565639 www.national.com 8 LF412 Pulse Response RL=2 k, CL=10 pF Current Limit (RL=100) (Continued) 00565640 Application Hints The LF412 series of JFET input dual op amps are internally trimmed (BI-FET IITM) providing very low input offset voltages and guaranteed input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will cause a reversal of the phase to the output and force the amplifier output to the corresponding high or low state. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output, however, if both inputs exceed the limit, the output of the amplifier may be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on 6.0V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 k load resistance to 10V over the full temperature range. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize "pick-up" and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. 9 www.national.com LF412 Typical Application Single Supply Sample and Hold 00565631 www.national.com 10 LF412 Physical Dimensions unless otherwise noted inches (millimeters) Metal Can Package (H) Order Number LF412MH, LF412MH/883 or LF412CH NS Package Number H08A 11 www.national.com LF412 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Dual-In-Line Package (J) Order Number LF412MJ/883 NS Package Number J08A Dual-In-Line Package (N) Order Number LF412ACN or LF412CN NS Package Number N08E www.national.com 12 LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. This datasheet has been download from: www..com Datasheets for electronics components. |
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